The present invention is directed generally to semiconductor devices and methods of fabrication and more particularly to a charge storage thin film transistor array and method of fabrication.
U.S. published application 20020028541 which was filed as U.S. application Ser. No. 09/927,648, on Aug. 13, 2001 and which is incorporated by reference in its entirety, discloses a monolithic three dimensional array of charge storage devices. In one embodiment in this application, the charge storage devices of the array comprise both top gate staggered and inverted (i.e., bottom gate) staggered thin film transistors. Thin film transistors are called xe2x80x9cstaggeredxe2x80x9d when the gate electrode is located on the opposite side of the active layer from the source and drain electrodes. In the inverted staggered thin film transistors, the active layer and the bit lines were both made of polysilicon.
A preferred embodiment of the present invention provides a semiconductor device, comprising a gate electrode, a gate insulating layer located above the gate electrode, an active layer located above the gate insulating layer, an insulating fill layer located above the active layer, a first opening and a second opening located in the insulating fill layer, a first source or drain electrode located in the first opening, and a second source or drain electrode located in the second opening. At least one of the first and the second source or drain electrodes comprises a polysilicon layer and a metal silicide layer.
Another preferred embodiment of the present invention provides a monolithic, three dimensional array of thin film transistors, comprising a substrate an intermediate dielectric layer located above the substrate, a first planarized insulating fill layer located at a first height above the intermediate dielectric layer, a first plurality of openings located in the first planarized insulating fill layer and a plurality of first word lines located in the first plurality of openings in the first planarized insulating fill layer and extending in a first direction. The array further comprises a first gate insulating layer located above the first word lines and above the first insulating fill layer, a first active layer located above the first gate insulating layer, a second insulating fill layer located above the first active layer, a second plurality of openings located in the second insulating fill layer and first bit lines located in the second plurality of openings in the second insulating fill layer, wherein at least one of the first bit lines comprises a first polysilicon layer and a first metal silicide layer, and the first bit lines extend in a second direction different from the first direction. The array further comprises a second active layer located above the first bit lines and above the second insulating fill layer, a second gate insulating layer located above the second active layer, and a plurality of second word lines located above the second gate insulating layer, the second word lines extending in the first direction.
Another preferred embodiment of the present invention provides a method of making a semiconductor device, comprising forming a first gate line layer, patterning the first gate line layer to form a plurality of first gate lines, forming a first insulating fill layer over and between the first gate lines, planarizing the first fill layer coplanar with top surfaces of the first gate lines, forming a first gate insulating layer over the first gate lines and the first fill layer, forming a first active layer over the first gate insulating layer and forming a second insulating fill layer over the first active layer. The method further comprises patterning the second insulating fill layer such that first portions of the first active layer are covered by the second insulating fill layer and openings in the second insulating fill layer expose second portions of the first active layer, forming a first source/drain line film comprising a first polysilicon layer and a first metal silicide layer in the openings in the second insulating fill layer, and planarizing the first source/drain line film such that first source and drain electrodes remain in the openings in the second insulating fill layer, and top surfaces of the first source and drain electrodes are coplanar with a top surface of the second insulating fill layer.
Another preferred embodiment of the present invention provides a method of making an inverted staggered thin film transistor, comprising forming a gate electrode, forming a gate insulating layer over the gate electrode, forming an active layer over the gate insulating layer, forming an insulating fill layer over the active layer, patterning the insulating fill layer such that first portions of the active layer are covered by the insulating fill layer and openings in the insulating fill layer expose second portions of the active layer, forming a source/drain line film comprising a first polysilicon layer and a metal silicide layer in the openings in the insulating fill layer, and planarizing the source/drain line film such that source and drain electrodes remain in the openings in the insulating fill layer, and top surfaces of the source and drain electrodes are coplanar with a top surface of the insulating fill layer.